Flash memory is a type of semiconductor computer memory with many desirable characteristics. Like read only memory, ROM, it is non-volatile, meaning that the contents of the memory are stable and retained without applied electrical power.
Flash memory devices have found wide commercial success in the electronic device market. A major advantage of flash over ROM is that the memory contents of flash may be changed after the device is manufactured. Flash memory has found wide acceptance in many types of computers, including desktop computers, mobile phones and hand held computers. Flash memory is also widely used in digital cameras and portable digital music players, for example “MP3” players.
In addition to direct flash storage applications, for example in video cameras, flash-based storage devices are replacing rotating magnetic disks, sometimes known as hard drives, in many applications. Compared to hard drives, flash is significantly more rugged, quieter, lower power, and for some densities such a flash based device may be smaller than a comparable hard drive.
FIG. 1 shows a memory cell 10 as has been well known in the conventional art. Regions 14 are the drain and/or source regions for memory cell 10. They may be used as source and/or drain interchangeably. Control gate 16 is used to control the operation of memory cell 10. A channel region 17 is formed between source/drain regions 14. Feature size 18 is the nominal size of the smallest feature that can be created by a particular semiconductor process. In memory cells of this type, the gate 16 width and channel 17 length typically correspond approximately to feature size 18.
Memory cell 10 may be one of two general types of non-volatile memory, a “floating gate” cell or a nitride read only memory (NROM) cell. In a floating gate cell, layer 12B of the gate stack is typically conductive polysilicon. Layers 12A and 12C are insulating materials which isolate or “float” gate layer 12B, which is usually referred to as a floating gate. Floating gate 12B is the storage element of memory cell 10.
Silicon nitride based flash memory has many advantages as compared to its floating gate and tunneling oxide based counterparts. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is potentially very dense in terms of number of cells per unit area that can be used and it requires fewer process steps as compared to floating gate memory. Moreover, it can be easily integrated with standard SRAM process technology. A further advantage of using SONOS devices is their suitability for applications requiring large temperature variations and radiation hardening. The SONOS stack is a gate dielectric stack and consists of a single layer of polysilicon, a triple stack ONO (Oxide-Nitride-Oxide) gate dielectric layer and a MOS channel 17. The ONO structure may consist of a tunnel oxide 12A, a nitride memory storage layer 12B and a blocking oxide layer 12C.
Flash memory devices are typically configured as an array of many instanced of individual cells, e.g., cell 10, oriented in rows and columns. Typically, the control gates, e.g., control gate 16 of FIG. 1, of the cells in each row are connected to a series of word lines, thus forming individual rows of cells that can be accessed by selecting the corresponding word line. Similarly, the source and/or drain, e.g., regions 14, of the cells in each column are connected to a series of bit lines, thus forming individual columns of cells that can be accessed by selecting the corresponding bit lines.
Memory device manufacturers are continually challenged to provide ever greater amounts of memory at ever lower costs. Recently, Advanced Micro Devices, Incorporated of California has introduced MIRROR BIT™ nitride-based flash ROM that stores multiple bits per memory cell 10 physically separated in nitride layer 12B. Such storage of multiple bits per cell increases the storage density of the memory device, thereby reducing the cost per bit of storage.
To read a bit stored in the “left” portion of memory cell 10, a word line is brought to a read voltage of about 4.5 volts and a bit line is grounded. Node 14A (the “left” instance of regions 14) functions as a source for the cell, and current flows from node 14B, acting as a drain, to node 14A through a bit line to ground. Sensing logic connected to the bit line can interpret the magnitude of the current (which is affected by the amount of charge stored in nitride gate layer 12B) in order to determine if a bit is stored in the “left” portion of cell 10.
To read a bit stored in the “right” portion of memory cell 10, a word line is brought to a read voltage of about 4.5 volts and a bit line is grounded. Node 14B (the “right” instance of regions 14) functions as a source for the cell, and current flows from node 14A, acting as a drain, to node 14B through a bit line to ground. Sensing logic connected to the bit line can interpret the magnitude of the current (which is affected by the amount of charge stored in nitride gate layer 12B) in order to determine if a bit is stored in the “right” portion of cell 10.
To write (or program) a bit into the “right” portion of memory cell 10, a line is brought to a programming voltage of about 9.5 volts, and a bit line is grounded and acts as a source. Current is sourced from the word line through node 14A into bit line. The current causes hot carrier injection of charge into the nitride layer of the SONOS stack in physical proximity to node 14A.
To write (or program) a bit into the “left” portion of memory cell 10, a line is brought to a programming voltage of about 9.5 volts, and a bit line is grounded and acts as a source. Current is sourced from the word line through node 14B into bit line. The current causes hot carrier injection of charge into the nitride layer of the SONOS stack in physical proximity to node 14B.
However, flash memory generally can not be written to, or programmed, at rates comparable to random access memory, RAM, or at rates directly compatible with a computer system's processing unit. Consequently, the benefits of flash, e.g., changeable non-volatile storage, demand a deleterious decrease in write performance of the memory subsystem. In addition, as most computer systems utilizing flash memory also employ RAM, the complexities of managing the differing timing requirements between flash and RAM are an undesirable burden on system designers seeking to utilize flash memory. Further, flash generally must be erased, either in its entirety or in large segments called pages, prior to changing its contents. Erasing a flash device, or a portion of a flash device, is generally a long process, typically measured in hundreds of milliseconds. This is a disadvantage compared to RAM and hard drives, which may be written directly, without an interposing erasure.
There have been numerous techniques employed in the conventional art to improve either the actual or apparent programming/write speed of flash memory. For example, segments of a flash memory device may be pre-erased so that the portion(s) are erased and ready to be programmed immediately when desired. An approach used to hide the programming time required for flash memory increases the apparent write speed of flash memory by caching write data into a RAM buffer, and utilizing a background process to actually erase and/or program the flash memory. This is a conventional function of software commonly known as a “flash file system.”
In another conventional attempt mitigate the write speed disadvantage of flash, some flash devices are capable of partial page programming. Partial page programming is a technique whereby some of the contents of a page of flash memory may be updated without erasing. Typically, a cell of flash memory is described as being either in the erased state or the programmed state. Either state, programmed or erased, may be arbitrarily assigned the binary value 0, and the other state may be assigned the binary value 1.
Assuming the erased state is assigned the binary value 1, partial page programming generally allows, for example, instances of 1 in the programmed page to be changed to a value of 0, without an intervening erase process. In general, cells programmed to a value of 0 may not be changed to a 1 value. Changing a cell from a 0 to a 1 typically requires the page or block erase process.
Many of these conventional approaches to increasing the write performance of flash memory rely primarily on software-implemented processes to manage flash storage. The use of additional software, e.g., a flash file system, may be undesirable as it increases the computational load of a host processor, and generally requires additional storage, both for buffers and other data tables required to implement the processes as well as for software code storage. In many computer systems, especially hand held computer systems, the cost of such increased storage may be burdensome. Further, the increased complexity of memory accesses contributes to memory storage errors and an undesirable increased development effort on the part of the designers.
Semiconductor processing equipment is extremely expensive. Fundamental semiconductor processing steps, e.g., implantation and diffusion, typically require long periods of development and extensive qualification testing. Implementing a new fabrication process requires considerable resources on the part of the semiconductor manufacturer. A manufacturer may have to alter or entirely revamp process libraries and process flows in order to implement a new fabrication process. Additionally, re-tooling a fabrication line is very expensive, both in terms of direct expenses as well as in terms of opportunity cost due to the time required to perform the re-tooling. Consequently, any solution to increase the rate of flash programming should be compatible with existing semiconductor processes and equipment without the need for revamping well established tools and techniques.
Accordingly, a need exists to increase the programming speed of flash memory. A further need exists for increasing the programming speed of flash memory in a manner that is compatible and complimentary with conventional approaches to increase the programming speed of flash memory. A still further need exists for the above mentioned needs to be achieved with existing semiconductor processes and equipment without revamping well established tools and techniques.